Since their commercial introduction a half century ago, many types of integrated circuit (IC) devices have been developed, and they now are widely used in consumer electronics, military, medical, and industrial applications. During portions of the manufacturing process of an integrated circuit device, as well as afterwards, it often desirable to test the device to verify that it works properly.
Design-for-test (“DFT”) techniques employing scan circuits and automatic test pattern generation (“ATPG”) are commonly used as part of integrated circuit manufacturing to provide high test coverage as well as to reduce test cost. In scan-based testing, memory elements embedded in integrated circuit devices (sometimes referred to as “scan cells”) are arranged in series to form one or more scan chains. The scan chains are connected to functional logic within the integrated circuit device so that the scan chains can apply signals values to the functional logic, and so that signal values produced by the functional logic can be stored in the scan cells of the scan chain.
A test pattern generated for scan-based design typically is applied as follows. The tester loads the test values of the test pattern into the scan chain through a scan shifting operation. During the scan shifting operation, the test values are sequentially passed from scan cell to scan cell, until the test values are located in their designated scan cells along the scan chain. The shifting operation is followed by one or more clock cycles, called capture cycles, during which test values are applied to the function logic, and the values produced by the functional logic in response are captured by the scan cells. Finally, the test responses are sequentially unloaded from the scan chain through another scan shifting operation for subsequent analysis. Typically, the test values are loaded from an automatic test pattern generation (ATPG) tool, and the test responses are output to the ATPG tool.
The scan tests generated by a typical ATPG tool, however, can create switching activity on the integrated circuit that far exceeds the activity present during normal operation of the circuit. Excessive switching activity can be created when a scan test causes the device-under-test to operate outside of its normal functional operation. Furthermore, excessive switching activity can occur during several stages of the testing operation. For example, excessive switching can occur when the scan chain is loading a test pattern, unloading a test response, or when its scan cell contents are updated during the capture cycles. The excess power consumption raises the device temperature, sometimes high enough to damage the device. High switching activity also causes voltage droops on signal lines that result in slower performance of the chip, and misidentification of a good device as defective.